The present invention is related to U.S. patent application Ser. No. 08/336,543, filed Nov. 9, 1994, entitled "High Performance Dynamic Compare Circuit", and Ser. No. 08/336,524, filed Nov. 9, 1994, entitled "A Charge Shared Precharge Scheme to Reduce Compare Output Delay," and hereby refers to, and incorporates by reference the content of the above referenced applications herein.
1. Field of the Invention
The present invention is related to the field of data processing systems, and more particularly, the present invention relates to filter circuits for use with digital memories and other devices which require the use of sense amplifiers.
2. Art Background
There are many instances in modem data processing systems wherein a central processing unit (CPU) or other device must determine whether or not two data words are identically equal. For example, a comparison operation between a first and a second data word may be required in the case of a cache memory system in which data words and/or memory tags must be compared, as well as in other digital systems such as encryption devices wherein passwords and the like must be compared for an identical match.
In many instances, at least one of the digital words to be compared may be read by the CPU from memory. As is known, digital memory devices are comprised of electronic memory cells which store either a logical zero or a logical one. To read a cell, the voltage level of the cell must be sensed to determine its logical state. The sensing of the cell is accomplished through the use of sense amplifiers. A natural characteristic of electronic sense amplifiers is that their output voltage may dip prior to providing a final "solid" voltage output level. As will be described, this natural voltage dip may result in spurious signals including false hit or miss conditions during a compare operation.
The present invention provides an improved common mode dip filter circuit, which has particular application for use in electrical circuits wherein sense amplifier voltage dips must be filtered to avoid false hits or misses. Although the present invention will be described with reference to its current implementation in a high performance dynamic compare circuit, it will be appreciated that the present invention may be utilized in a variety of other circuit applications.